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  • plopke - Wednesday, May 16, 2018 - link

    Aaah this article reminds me of HP memristor , "100TB drives by 2018" , "it will replace Flash and in some cases RAM". So far the only one coming close is Intel/Micron but a few years of delay , well lets hope these guys make it and are not held back by patents or lack of mass production to bring it to market!
  • ImSpartacus - Wednesday, May 16, 2018 - link

    Yeah, we've been burnt so many times by overzealous claims that I've become rather pessimistic about new memory tech.

    Obviously I hope for the best, but I'm not holding my breath.
  • mode_13h - Friday, May 18, 2018 - link

    Burnt? You had some financial stake in any of these promises?

    No need to get "burnt" this time - they aren't even claiming the same performance levels as 3D XPoint, so keep your expectations in check. Write latencies around 10 microseconds puts this more on par with NVMe flash.
  • Santoval - Monday, May 21, 2018 - link

    True, write latencies are comparable to flash but read latencies are 1000 times faster, about as fast as L2 cache. So ReRAM could be employed in read-intensive workloads (in place of the pitifully slow QLC flash, which also has a pathetic endurance) - if they manage a high enough density. ReRAM's performance is highly .. asymmetric, but if you can have the write speed of flash with the read speed of L2 cache it is not a bad deal at all.
  • wumpus - Friday, May 18, 2018 - link

    You're reading the wrong things into this. As stated, ReRam can't compete with either Flash or DRAM for storage, so they really aren't trying to sell to *you*. They are selling it to ASIC designers who don't want to pay for an extra chip on the board, nor the extra pins and connections.

    Putting memory on a chip is a pain. For small sizes, just slap down 6 transistors for a SRAM bit and go. You can pretty much expect to find this anywhere you need to scatter storage in the chip, and famously in the caches of CPUs.

    I'm guessing that they can access ReRAM far easier than Flash (which has to be read in fairly large batches and written [well erased] in huge batches). DRAM on a chip is also problematic, in that the transistors themselves don't really match the logic processes that ASICs use (check the sizes sometime: embedded DRAM transistors are something like 10 times as big, and use a vastly smaller process). DRAM has enough overhead (all the sensors and such, but I suspect that ReRAM is at least as bad) that when combined with the extra-large transistors you tend to only cram twice the memory in the same [large] area as SRAM. Presumably ReRAM beats this.

    But comparing embedded ReRAM to DRAM made on a DRAM chip or large amounts of FLASH? Won't happen and this article says as much. You won't see it in your computer (soon), you won't see it in your phone, you *might* see it in the embedded processor in your toaster.

    Still, if they can ship a product they can keep the labs running. And who knows what type of advantages it might have at 0xnm.
  • Dragonstongue - Wednesday, May 16, 2018 - link

    cheers to this...maybe this will allow lower cost higher performance memory for SSD, RAM or whatever they can envision, we NEED competition in the tech industry to keep prices "honest" afterall ^.^
  • mode_13h - Friday, May 18, 2018 - link

    Go back and re-read the article!

    This is neither about density nor $ per GB! It's about low read latency, high endurance (relative to NAND), and long retention.
  • MrSpadge - Wednesday, May 16, 2018 - link

    Yeah, HP was very bold with its claims back then. And there's good reason to be sceptic about any new memory technology. They may be excel in 2 or 3 attributes, but lack in another important one. That's enough to keep them from taking over the market or even entering it. However, I would say Crossbar is above average in this regard. Several factors are aligning favorably, so they may actually succed in some ways.
  • BubbaJones - Monday, April 15, 2019 - link

    Pretty crazy being approached recently by old friends (architects) in the PCM biz, asking if I had ideas how to better use a bunch of 3DXPoint managed behind a NVMe front end. Well, when your low-level PCM device interface is ill-conceived it's really hard not to aggregate as anything but a block device. Like storage protocols before NVMe, we already figured out how to hide latency. 3DXPoint doesn't buy you that much. Should have listened...now back to the drawing board boys.

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