The Microprocessor: Revolutionary New Architecture: Dream or Reality?by Anand Lal Shimpi on August 13, 1998 3:06 PM EST
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A few months back AnandTech conducted a series of tests on the current processors out at the time for the Evolution of the Microprocessor Article. By making sure all processors had their L1 and L2 caches clocked at equivalent (or close to equivalent) speeds, and by essentially leveling the playing field we managed to make a few interesting discoveries about your favorite CPU's. For one thing, the Pentium II, by default, disables its on-board L2 cache if you exceed its locked Clock Multiplier Setting and also configures itself with a 2.0x multiplier setting. We also discovered that, at the lowest of levels, the Cyrix 6x86MX turned out to be the best overall processor however we also managed to illustrate the poor FPU performance of non-Intel processors in spite of their manufacturer's claims of improved performance.
There were a few flaws in the original testing brought on by limitations of motherboards and the CPU's available at the time. The Pentium II operated its memory bus at 83MHz while the rest of the processors kept their memory bus at 66MHz, also the Pentium II was crippled in some tests due to its automatic disable of its on-board L2 cache. This time the bridge between CPU architectures and interfaces can be crossed much easier with the advent of the Super7 motherboard platform and the 100MHz Front Side Bus (FSB).
Chips & Bits
How can you compare a processor that interfaces with the motherboard via a Socket to a processor that interfaces with the motherboard via a Slot? It's actually quite simple, with a little help from a motherboard standard called Super7. The VIA MVP3 Chipset allows for the memory bus to be operated at an external frequency locked to the frequency which the AGP bus operates at. In the case of the tests AnandTech ran on the processors for this article, the AGP bus ran at 2/3 of the speed of the FSB which was clocked at 100MHz, making the AGP and Memory Buses run at 66MHz. Now keep in mind that because of the 100MHz FSB the L2 cache of the Super7 test system was operating at 100MHz, and for the sake of comparison all processors were clocked at 200MHz. Why? Well, let's take a look at the Pentium II to find out.
Leveling the playing ground is a difficult task when the Pentium II is brought into the game, the Pentium II derives its L2 cache speed from the Clock Speed of the CPU, not from the FSB speed. The L2 cache on a Pentium II operates at 1/2 of the clock speed, so in order to keep things fair the Pentium II would have to run at 200MHz in order for it to be compared to the Super7 chips since a 200MHz P2 would run its cache at half the clock speed, or 100MHz. Although the Intel 440BX chipset doesn't allow for operation of the memory bus at the speed of the AGP bus, we can simulate the same effect on the ABIT BH6 BX Motherboard used for the Pentium II tests. While all of the Super7 processors ran at the 100MHz FSB x a 2.0 clock multiplier, with the Memory Bus running at 66MHz the Pentium II test system ran at the 66MHz FSB x a 3.0 clock multiplier which kept the memory bus at 66MHz while the L2 cache still operating at 1/2 the clock speed, being 100MHz.
A Truly "Fair" Comparison
As discussed in the original Evolution of the Microprocessor Article, you may believe that in order for a fair comparison one would have to disable the L1 cache on all the processors, however doing so is penalizing a processor for being "itself," the way its manufacturer intended it to be. For example, the Pentium II mutates from a hideously fast daemon to a mere tortoise when you take away its precious L1 cache, to put it into perspective, imagine running Win95 on a 286..it isn't pretty, try running it on a Pentium II without L1 cache...the scene isn't all that different. So none of the processors were penalized for any enhancements that happened to be included in the physical die of the chip (the actual chip, not any additional enhancements made outside of the chip's packaging) since you can't order a 6x86MX with only 32KB of L1 cache and you can't order a Pentium II with 64KB of L2 (not yet at least), the L1 cache is part of the processor so it would be unfair to disable it.