TSMC has quietly introduced a performance-enhanced version of its 7 nm DUV (N7) and 5 nm EUV (N5) manufacturing process. The company’s N7P and N5P technologies are designed for customers that need to make then 7 nm designs run faster, or consume slightly lower amount of power.

TSMC’s N7P uses the same design rules as the company’s N7, but features front-end-of-line (FEOL) and middle-end-of-line (MOL) optimizations that enable to either boost performance by 7% at the same power, or lower power consumption by 10% at the same clocks. The process technology is already available to TSMC customers, the contract maker of chips revealed at the 2019 VLSI Symposium in Japan, yet the company does not seem to advertise it broadly.

N7P uses proven deep ultraviolet (DUV) lithography and does not offer any transistor density improvements over N7. Those TSMC clients that need a ~ 18~20% higher transistor density are expected to use N7+ and N6 process technologies that use extreme ultraviolet (EUV) lithography for several layers.

While both N7 and N6 will be ‘long’ nodes that will be used for years to come, TSMC’s next major node with substantial density, power, and performance improvements is N5 (5 nm). The latter will also be offered in a performance-enhanced version called N5P. This technology will also feature FEOL and MOL optimizations in order to make the chips run 7% faster at the same power, or reduce consumption by 15% at the same clocks.

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Source: WikiChip.Org

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  • Rudde - Tuesday, July 30, 2019 - link

    What is the downside? Is it more expensive per chance, or does it launch later? Why don't they jump straight to it on 5nm?
  • Gondalf - Wednesday, July 31, 2019 - link

    5nm likely is right now is a disaster for power density and leakage on high power SKUs.
    Looking at Ryzen 2 core temperatures, i have some doubts the suboptimal power savings of 5nm are enough to compensate the higher temperature spikes on silicon and the temperature leakage that severly limit right now the ability to clock high all cores up on the 7nm tech showed on Zen 2.
  • psychobriggsy - Wednesday, July 31, 2019 - link


    Refinement that comes with time.
  • Rudde - Wednesday, July 31, 2019 - link

  • deil - Wednesday, July 31, 2019 - link

    stability, usually more mature nodes have better yelds, its all end up more/less that bleeding edge have twice the cost of last gen.
    if they can offer same hardware, new tweaks -> better thing, at almost no cost. its not that bad of a deal, as long as you dont have to be top of the top.
  • name99 - Wednesday, July 31, 2019 - link

    TSMC is a FOUNDRY!!!
    Read that sentence ten times!!!

    This means that they are NOT in the business of "leading edge and nothing else"; they are in the business of giving customers what's useful. And TSMC has MANY customers.

    So if you are starting a design from scratch, sure, target 5nm. But if you have an existing design you can tweak it just very slightly and get a nice almost free boost.

    People still use 28nm (let alone 45 or 65nm). They'll still be using 7nm many years from now. And if TSMC has, as part of their sales pitch, that they keep improving even the non-leading processes, well, that helps keep customers happy.
  • RSAUser - Thursday, August 1, 2019 - link

    5nm isn't as refined yet, so you'll have more bad chips per wafer, pushing up costs, with probably lower performance, and it would have more issues binning as less chips.

    7nm is already known and refined, so you know what the yields are, your architecture is tweaked to take advantage of the node, etc.

    It would take a bit before they move to 5nm, maybe 2020 on some special, lower power parts, with 2021 probably hitting mainstream. It takes a couple of years from first customer orders with tests to actual launch in the customer's hands, TSM already had customer trials of 7nm end of 2017, and you've only seen 7nm parts in 2019, expect something similar for 5nm.
  • azfacea - Tuesday, July 30, 2019 - link

    ryzen 4000 5GHz yay
  • LordSojar - Tuesday, July 30, 2019 - link

    It, unfortunately, doesn't quite work that way. Maybe, yes, but then, maybe not. Gate leakage increases with smaller and smaller pitch sizes. So... It's more about making each core do more, rather than go faster. Faster is good, more efficient at doing the same per cycle is better.
  • boeush - Tuesday, July 30, 2019 - link

    There's work around new transistor architectures, to replace finfet while reducing leakage, improving density, lowering voltage/power, and reducing electrostatic lag: GAA, vertical nanowire, 3D-stacked complementary FET... All rumors to the contrary notwithstanding, we're still quite far from hitting the quantum wall, from the manufacturing side of things, in terms of improving processing density and performance. But yes, better processor architectures can be helpful also.

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