In this week's quarterly earnings conference call, TSMC’s revealed that the company expects most of its 7nm "N7" process customers to eventually transition to its forthcoming 6nm "N6" manufacturing node. The upcoming node will use the same design rules as the N7 node, making it easier for customers to transition to the newer, denser node. And, if TSMC's predictions come true, N6 is now on the path towards becoming another widely-utilized, long-serving process node for the company.

In comments made during the quarterly call, CC Wei, TSMC's CEO and vice chairman noted that “most of the customers in the N7 will move to N6.” In fact it sounds like TSMC's N6 node is set to become another one of TSMC's popular, high volume nodes, with Wei further stating that “from that day on probably, the N6 will pick up all the momentum and pick up all the volume production.”

As previously reported, TSMC’s N6 process technologies adopts extreme ultraviolet lithography (EUVL) to lower manufacturing complexity by reducing the number of exposures required for multi-patterning (which is needed today as TSMC’s N7 uses solely DUV lithography). While TSMC's N7+ uses up to four EUVL layers, its N6 expands it up to five layers, whereas N5 expands usage of EUVL all the way to 14 layers.

UPDATE: Correcting the number of EUV layers used by N6 and N7.

While TSMC’s N6 uses new production equipment and offers 18% higher transistor density than the company’s N7 manufacturing technology, N6 uses the same design rules as N7 and enables designers of chips to re-use the same design ecosystem (e.g., tools, etc.), which will allow them to lower development costs. By contrast, N7+ uses different design rules, but also provides more advantages than N6 when compared to N7.

Advertised PPA Improvements of New Process Technologies
Data announced by companies during conference calls, press briefings and in press releases
Power 60% 40% 60% <40% 10% ? 20%
Performance 40% 20% 30% ? same (?) ? 15%
Area Reduction none >50% 70% >37% ~17% ~15% 45%

While TSMC’s partners have adopted both N7 and N7+ processes and the world’s largest contract maker of chips expects the two technologies to contribute over 25% of its wafer revenue in 2019, the former looks to be somewhat more popular that the latter. Meanwhile, TSMC projects that most of its customers who use N7 today will migrate to N6 and then to N5 skipping the N7+. Considering how widespread N7 is going to get, N6 will likely be quite popular as well.

Related Reading:

Source: TSMC, Cadence

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  • Sychonut - Wednesday, May 1, 2019 - link

    Looking forward to Intel's 14+++++++.
  • valinor89 - Wednesday, May 1, 2019 - link

    Let's call it 14∞ and be done with it.
  • RSAUser - Thursday, May 2, 2019 - link

    I can't easily hit infinity on my keyboard, so that's a negative.
  • Dragonstongue - Thursday, May 2, 2019 - link

    ^ they should lol, this way here no one can truly complain as it will always fall in the ∞ numbering, I think the next best look for a simple numeral is omega Ω which of course would signify "the end" course in their case it just means a stopping ground to unload all them dead numbered bodies LOL
  • levizx - Friday, May 3, 2019 - link

    Then there is 14∞+
  • bug77 - Thursday, May 2, 2019 - link

    14# ;)
  • Ironchef3500 - Thursday, May 2, 2019 - link

    Aren't we all!
  • serendip - Wednesday, May 1, 2019 - link

    They're exploiting the mass effect already.
  • PeachNCream - Thursday, May 2, 2019 - link

    You mean they're telling us there won't be an A, B, or C ending but they're giving us an A, B, or C ending?
  • AshlayW - Wednesday, May 1, 2019 - link

    How likely is it that AMD's Zen2+ will be on this process instead of N7+?

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