JEDEC has published its UFS 3.1 specification (aka JESD220E), which adds several performance, power, cost-cutting, and reliability-related features to the standard. The new capabilities promise to increase real-world device performance, minimize power usage, potentially cut costs of high-capacity storage devices, and improve the user experience.

Devices compliant with the UFS 3.1 standard continue to use MIPI's M-PHY 4.1 physical layer with 8b/10b line encoding, MIPI’s UniPro 1.8 protocol-based interconnect layer (IL), and support HS-G4 (11.6 Gbps) per lane data rates. Meanwhile, the new version of the specification supports three new features: Write Booster, Deep Sleep, and Performance Throttling Notification. In addition, JEDEC published a specification for Host Performance Booster technology. All of these features are already supported by modern SSDs, so the UFS 3.1 spec and HP bring UFS storage devices closer to SSDs in terms of functionality.

As the name suggests, Write Booster is designed to increase write speeds by using a pseudo-SLC cache. A similar technology is already used with SSDs and various miniature NVMe-powered storage devices, such as those used in Apple’s iPhone/iPad. Also, caching is supported by the SD 6.0 standard to hit write performance targets.

The second important new capability of the UFS 3.1 technology is Deep Sleep, a new lower power state designed for cheap UFS devices that use the same voltage regulators for storage and other functions.

Yet another new capability is Performance Throttling Notification that enables the UFS device to inform the host about performance throttling when overheating. Ultimately, avoiding throttling means a more consistent performance.

Last but not least is Host Performance Booster, which caches the logical-to-physical (LTP) address map of a UFS device in the system’s DRAM to improve performance. Mobile applications use a lot of random read operations and therefore access LTP address maps often. Meanwhile, because storage capacity of UFS devices is growing, so is LTP size, which makes it harder (and more expensive) to keep it in a controller’s memory. By hosting LTP in fast system DRAM and delivering an LTP hint when sending an I/O request, it is possible to improve random read performance and reduce the cost of the UFS controller. Samsung worked on HPB feature several years ago and claims that it can improve random read performance by up to 67%. In SSDs, HMB capability is used to cut down costs, so HPB will prevent UFS devices from getting too expensive as their capacity increases. It is important to note though that HPB is not a mandatory, but an optional feature for now.

To sum things up, while UFS 3.1-compliant storage devices will continue to offer a theoretical maximum bandwidth of up to 23.2 Gbps (2.9 GB/s) when HS-G4 is used (given the encoding used by M-PHY 4.1, actual achievable bandwidth should be something like 1.875 GB/s). However, with Write Booster and HPB implemented, real-world performance of upcoming UFS drives will get higher and more consistent. Meanwhile, Deep Sleep will help to prolong battery life of lower cost devices.

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Source: JEDEC

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  • PeachNCream - Friday, January 31, 2020 - link

    Cool, but sort of a pity that UFS has not yet replaced eMMC across the board but there is a lot of "good enough" storage performance on tap for eMMC devices.
  • willis936 - Friday, January 31, 2020 - link

    Part of that is their heavy-handed walled garden. I used to work at a test house that likes to be present in many standards bodies. The UFS had utterly unreasonable requirements for members. You need have multiple engineers do free work for something like a year before they would consider inviting you. That isn't how standards bodies are run. I'm sorry, Samsung is big but it's not so big that other people will bend over backwards to be in their backyard. Open spec development is key for adoption.
  • milkywayer - Friday, January 31, 2020 - link

    That's cool and all but is there also a standard to stop laptop makers from making 4gb and 8gb laptops in the $1000-1500 range in 2020?
    Im looking at you Dell, with the new xps 13 with massive 4 gigs of ram going for $1000+ after taxes.
  • PeachNCream - Friday, January 31, 2020 - link

    The only way we're going to get there is t purchase something else. Sucks that 4GB of RAM is STILL finding its way into $1K laptops and there are quite a few models that continue to max out at 8GB. What year is it?
  • PeachNCream - Friday, January 31, 2020 - link

    I had no idea that was even a problem. Given JEDEC is the publishing entity, I would have thought there would be fewer barriers to participation in the UFS standards body. Thanks for sharing your insights.
  • Spunjji - Monday, February 3, 2020 - link

    Thanks for the perspective.
  • Santoval - Friday, January 31, 2020 - link

    "Devices compliant with the UFS 3.1 standard continue to use MIPI's M-PHY 4.1 physical layer with 8b/10b line encoding..."
    Why continue to waste 20% of the bandwidth for encoding when there are many other available, much more efficient encoding options? 128b/130b wastes just 1.5% but perhaps it is a bit complex for UFS (though if they employed PCIe 3.0 as the physical layer they would also use 128b/130b encoding).
    Alternatively they could use 64b/66b encoding, which is simpler and has an encoding waste of 3%. 64b/66b encoding is used by Thunderbolt, 10/100 Gigabit Ethernet and InfiniBand, among others.
  • willis936 - Friday, January 31, 2020 - link

    You can’t beat 8b10b for clock recovery reliability. 66b64b can still allow for high BER in worst case data. I had trouble getting ANY receiver to lock onto SSPRQ during PAM4 development.
  • linuxgeex - Sunday, February 2, 2020 - link

    8b/10b is an acknowledgement that UFS is targeting low-cost applications, where BER will be higher as a result of cost-cutting aka corner-cutting.
  • GreenReaper - Sunday, February 2, 2020 - link

    Maybe someone put a patent on the idea of using fewer bits. >_<

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