Faster, Cheaper, Power Efficient UFS Storage: UFS 3.1 Spec Publishedby Anton Shilov on January 31, 2020 10:30 AM EST
JEDEC has published its UFS 3.1 specification (aka JESD220E), which adds several performance, power, cost-cutting, and reliability-related features to the standard. The new capabilities promise to increase real-world device performance, minimize power usage, potentially cut costs of high-capacity storage devices, and improve the user experience.
Devices compliant with the UFS 3.1 standard continue to use MIPI's M-PHY 4.1 physical layer with 8b/10b line encoding, MIPI’s UniPro 1.8 protocol-based interconnect layer (IL), and support HS-G4 (11.6 Gbps) per lane data rates. Meanwhile, the new version of the specification supports three new features: Write Booster, Deep Sleep, and Performance Throttling Notification. In addition, JEDEC published a specification for Host Performance Booster technology. All of these features are already supported by modern SSDs, so the UFS 3.1 spec and HP bring UFS storage devices closer to SSDs in terms of functionality.
As the name suggests, Write Booster is designed to increase write speeds by using a pseudo-SLC cache. A similar technology is already used with SSDs and various miniature NVMe-powered storage devices, such as those used in Apple’s iPhone/iPad. Also, caching is supported by the SD 6.0 standard to hit write performance targets.
The second important new capability of the UFS 3.1 technology is Deep Sleep, a new lower power state designed for cheap UFS devices that use the same voltage regulators for storage and other functions.
Yet another new capability is Performance Throttling Notification that enables the UFS device to inform the host about performance throttling when overheating. Ultimately, avoiding throttling means a more consistent performance.
Last but not least is Host Performance Booster, which caches the logical-to-physical (LTP) address map of a UFS device in the system’s DRAM to improve performance. Mobile applications use a lot of random read operations and therefore access LTP address maps often. Meanwhile, because storage capacity of UFS devices is growing, so is LTP size, which makes it harder (and more expensive) to keep it in a controller’s memory. By hosting LTP in fast system DRAM and delivering an LTP hint when sending an I/O request, it is possible to improve random read performance and reduce the cost of the UFS controller. Samsung worked on HPB feature several years ago and claims that it can improve random read performance by up to 67%. In SSDs, HMB capability is used to cut down costs, so HPB will prevent UFS devices from getting too expensive as their capacity increases. It is important to note though that HPB is not a mandatory, but an optional feature for now.
To sum things up, while UFS 3.1-compliant storage devices will continue to offer a theoretical maximum bandwidth of up to 23.2 Gbps (2.9 GB/s) when HS-G4 is used (given the encoding used by M-PHY 4.1, actual achievable bandwidth should be something like 1.875 GB/s). However, with Write Booster and HPB implemented, real-world performance of upcoming UFS drives will get higher and more consistent. Meanwhile, Deep Sleep will help to prolong battery life of lower cost devices.
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- Samsung Launches Single-Chip uMCP Packages with LPDDR4X DRAM & UFS 3.0 Storage