N5

So far we have three products in the market built on TSMC’s N5 process: the Huawei Kirin 9000 5G SoC, found in the Mate 40 Pro, the Apple A14 SoC, found in the iPhone 12 family, and the Apple M1 SoC, which is in the new MBA/MBP and Mac Mini. We can now add another to that list, but it’s not a standard SoC: here we have IP for a SerDes connection, now validated and ready for licensing in TSMC N5. Today Marvell is announcing its DSP-based 112G SerDes solution for licensing. Modern chip-to-chip networking infrastructure relies on high speed SerDes connections to enable a variety of different protocols at a range of speeds, typically in Ethernet, fiber optics, storage, and connectivity fabrics. Current high-speed...

TSMC: We have 50% of All EUV Installations, 60% Wafer Capacity

One of the overriding central messages to TSMC’s Technology Symposium this week is that the company is a world leader in semiconductor manufacturing, especially at the leading edge process...

32 by Dr. Ian Cutress on 8/27/2020

TSMC Expects 5nm to be 11% of 2020 Wafer Production (sub 16nm)

One of the measures of how quickly a new process node gains traction is by comparing how many wafers are in production, especially as that new process node goes...

13 by Dr. Ian Cutress on 8/25/2020

‘Better Yield on 5nm than 7nm’: TSMC Update on Defect Rates for N5

One of the key metrics on how well a semiconductor process is developing is looking at its quantitative chip yield – or rather, its defect density. A manufacturing process...

107 by Dr. Ian Cutress on 8/25/2020

TSMC Details 3nm Process Technology: Full Node Scaling for 2H22 Volume Production

At TSMC’s annual Technology Symposium, the Taiwanese semiconductor manufacturer detailed characteristics of its future 3nm process node as well as laying out a roadmap for 5nm successors in the...

57 by Andrei Frumusanu on 8/24/2020

TSMC & Broadcom Develop 1,700 mm2 CoWoS Interposer: 2X Larger Than Reticles

With transistor shrinks slowing and demand for HPC gear growing, as of late there has been an increased interest in chip solutions larger than the reticle size of a...

17 by Anton Shilov on 3/4/2020

TSMC Boosts CapEx by $1 Billion, Expects N5 Node to Be Major Success

TSMC is on track to begin high-volume production of chips using its 5 nm technology in the coming months, the company said in its conference call last week. While...

40 by Anton Shilov on 1/22/2020

TSMC: 5nm on Track for Q2 2020 HVM, Will Ramp Faster Than 7nm

TSMC’s 5 nm (N5) manufacturing technology is projected to provide significant benefits when it comes to performance, power, and area scaling, which is why the contract maker of semiconductors...

27 by Anton Shilov on 10/23/2019

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

Forecasting strong demand for its 5 nm and 7 nm class process technologies in the coming years, TSMC has announced that it's increasing its capital expenditure for 2019 by...

18 by Anton Shilov on 10/18/2019

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