Haswell: Up to 128MB On-Package Cache, ULV GPU Performance Estimates
by Anand Lal Shimpi on September 12, 2012 12:26 PM EST- Posted in
- CPUs
- Intel
- Haswell
- Trade Shows
- IDF 2012
Intel was surprisingly quiet about the remaining details of Haswell at IDF this year. We know the rough CPU architecture details, some info at a high level about the GPU and of course the platform power improvements. There is a lot more however.
We already know that in its quad-core GT3 configuration, Haswell will offer 2x the GPU performance of Intel's HD 4000 (Ivy Bridge GT4). What Intel didn't say however is that Haswell's ULV GT3 parts will offer around 30% better GPU performance than Ivy Bridge ULV GT2.
The improved graphics performance comes both from an updated architecture and more EUs, but also an optional on-package cache of up to 128MB in size. It's too early to talk about SKUs and DRAM configurations, but 128MB is the upper bound. Expect to see tons of bandwidth available to this cache as well.
On the CPU side you can expect a ~10% increase in performance on average over Ivy Bridge. As always we'll see a range of performance gains, some benchmarks will show less and others will show more.
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B3an - Wednesday, September 12, 2012 - link
If this is just normal DRAM used for the cache can someone explain to me how this can boost the performance? Unless it's very fast DRAM thats much faster than system memory.ImSpartacus - Wednesday, September 12, 2012 - link
Nothing is set in stone, but Mr. Shimpi said to expect buckets of bandwidth, so we probably shouldn't worry about effective speeds.CaedenV - Wednesday, September 12, 2012 - link
Cache is typically much faster (though much smaller) than DRAM. It does not help with anything, but the things it will help with will see vast improvements over relying on 'slow' system memory.CaedenV - Wednesday, September 12, 2012 - link
*everything, not anything... oopsDanNeely - Wednesday, September 12, 2012 - link
Rumors from a year ago were that Intel was going to use a large number of cellphone/tablet/etc type ram chips and implement a silicon interconnect (much denser traces than with a PCB) inside the package to create an ultrawide data bus to compensate for the low clockrates of each individual chip.With Haswell topping out at only 128Mb vs the 512mb-1gb being speculated about at the time it seems likely they've either scrapped the ultrawide bus, or are using a custom ram chip design with a much wider than normal databus instead of a commodity part.
extide - Wednesday, September 12, 2012 - link
That wasnt a rumor it was pure speculation.Kevin G - Wednesday, September 12, 2012 - link
The idea is the same as the eDRAM in the Xbox 360: store the frequently used buffers in the eDRAM to free up bandwidth to main memory while simultaneously giving access to those buffers a massive increase in performance. The performance benefits can be massive depending on how frequently those buffers are accessed and if they can contain the full buffer.With 128 MB, that's enough for two full 32 bit buffers at 1920 x 1080 resolution.
Kevin G - Wednesday, September 12, 2012 - link
Whoops, math fail. That'd be sixteen 32 bit buffers or eight 64 bit HDR buffers at 1920 x 1080 resolution.madmilk - Wednesday, September 12, 2012 - link
Being on-package allows the bus to be much wider. If rumors of the silicon interposer are true, there could potentially be a 512 bit (or wider) bus. Also, without wires travelling off the package, latency and power consumption are hugely cut down.jwilliams4200 - Wednesday, September 12, 2012 - link
Did you mean "Ivy Bridge GT2" instead of "Ivy Bridge GT4"? I don't think IvB has GT4 or GT3.