For our audience that regularly keeps track of Intel’s product portfolio, it would be hard to miss that the naming strategy of Intel’s process node technologies is a bit of a mess. To some, those words are themselves an understatement, as Intel has shifted its naming strategy 2-3 times since the launch of Intel’s first 10nm products. Not only that, even Intel’s various departments internally have a hard time keeping track of ‘what is this manufacturing process being called today’ when the press like AnandTech ask for details on the latest upcoming products.

Knowing this, and knowing what issues Intel has been having, I wanted to demystify Intel’s manufacturing process naming scheme such that users and engineers alike, even if they are inside Intel, can understand what is what but also importantly why. The why is the crucial factor.

If you're looking for a handy decoder ring for Intel's 10nm Products, it's here in page 3.

Why Do We Have Multiple Versions of a Process?

With Intel’s 14nm, we were invited to 14nm, 14+, 14++, 14+++, and if you believe Intel’s own slides, there were variants that went beyond this ++++ naming scheme. Each one of those additional + points on the end of the name signified a change in the process technology – usually to assist for increasing performance or efficiency.

Each one of these + points is an update to the BKM, or Best Known Methods.

While an engineer can draw an electrical layouts for a part of a processor, such as an addition circuit, actually applying that design to a silicon floorplan for manufacturing is a different skill altogether. Transistor libraries are designed to take advantage of a given process, and when a floorplan is optimized for a process, it can then be pasted and repeated as necessary – on top of this, simulation on thermals, power, and current density are applied to ensure that there are no hotspots or that critical paths inside the design have as few bottlenecks as possible.

When an update to the BKM occurs, two things can happen. Normally we see the update on the level of the transistor library that is changed – if the distance between two fins on a transistor increases for example, the transistor library and the macros may be made bigger, and then the floorplan might be redesigned to take account for this. As for any process node design, there are 100 different controls, and improving one might make three other controls worse, so it is a fine balancing act. Not only this, but the BKM has to be validated at the manufacturing level. The BKM update could apply to the metal stack as well, which in of itself can adjust the performance.

Lots of dials at each stage

In the long long past, BKM updates were never advertised externally. If Intel or TSMC or another foundry discovered a way to improve the performance, or decrease the voltage, or improve the yield, the update was silently rolled into the design and nothing much was made of it. Sometimes processors would be listed as ‘1.0 volts to 1.35 volts’, and it would just be a roll of the dice if a user obtained one of the lower voltage models.

However, as time between different process node updates has elongated, these BKM updates have started to be identified and effectively monetized by the semiconductor companies. An update to a process that improves the voltage by 50 millivolts and increases frequency by 200 MHz immediately becomes a productizable event, and products built on these updates can be offered for more money over the usual. Or, depending on the rate of updates, the whole next generation of products could be built on the update.

So we never saw BKM updates officially announced at Intel’s 45nm, 32nm, or 22nm process nodes. These updates were fast enough that the productization of any update didn’t warrant a full round of marketing. With 14nm, that changed.

Intel had discussed its roadmap beyond 14nm since its 2010 Investor Meeting. It predicted that the company would be on 14nm by 2013, 10nm by 2015, and 7nm by 2017. As we now know, 14nm was two years late, and 10nm was 2-4 years late. Because of the introduction of 10nm being delayed, Intel decided to productize its 14nm BKM updates, and signified those with + points.

Intel’s current official line is that there have been four updates to 14nm, creating five ‘generations’.

More Plus Means More Meme

Because of all the + points, Intel’s marketing sometimes getting it wrong, and perhaps a little bit of ‘++’ in most programming languages meaning ‘+1’, the whole concept of adding + to the process node has become a meme – a meme at Intel’s expense, purely on the basis of its failure to deliver 10nm before the 14++++ naming scheme got out of hand.

10nm Changes Direction, Twice
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  • drexnx - Friday, September 25, 2020 - link

    except that's categorically untrue. Each revision of the 14nm process has improved upon the previous, notably so.

    look at how poorly the initial Broadwell clocked and scaled (they didn't even release mainstream performance 5xxx chips!) vs. Cannon Lake and tell me they're the same process.
  • drexnx - Friday, September 25, 2020 - link

    er, vs. Rocket lake not Cannon lake.

    (too many lakes...)
  • AMDSuperFan - Friday, September 25, 2020 - link

    Where can I compare the Rocket Lake? Maybe you have the insider know how?
  • Smell This - Friday, September 25, 2020 - link

    Kaby 14nm 'backed-up' from the original design, and Chipzillah dumped tock-tick for **PAO**

    When you say, "Each revision of the 14nm process has improved upon the previous" ... that would be incorrect.
  • dotjaz - Friday, September 25, 2020 - link

    Except you can wrong and it does mean something. They have different design rules FFS. You can't just call it 14nm when in reality you must redesign and tape out again.
  • dotjaz - Friday, September 25, 2020 - link

  • Spunjji - Friday, September 25, 2020 - link

    Agreed. 10a, 10b etc. would also work.
  • jamesindevon - Friday, September 25, 2020 - link

    Ian, you are being way too polite to Intel.

    I don't blame you: you want to keep your contacts fairly happy. But Intel have now reached a point where customers just can't tell what they're buying.

    It's not just the process names. It's not just the crazy numbering scheme, although if it wasn't for, it would be.

    We've long had the situation where laptop OEMs can change the effective performance of a processor by changing the effective TDP, but with Tiger Lake Intel have been taking things way further. We're now at the position where it is effectively impossible to choose between laptops based on performance, because you just can't tell how the processor will perform. The OEMs won't tell you how they've configured their laptops beyond a processor model number.

    I, for one, am giving up on Intel marketing. If I want performance I can be fairly sure about, it looks like I have to buy AMD (and they're not as consistent as they should be, due to different laptop thermals. They don't have the option there: Intel do, but aren't taking it.)

    Jerry Pournelle once wrote that "years ago when AT&T tried to market PC's I said that if they bought Colonel Sanders they'd advertise hot dead chicken." Intel seem to have forgotten that dig.
  • ikjadoon - Friday, September 25, 2020 - link

    >We're now at the position where it is effectively impossible to choose between laptops based on performance, because you just can't tell how the processor will perform.

    Intel's misleading and backhanded TDP tactics aside: "the CPU model doesn't tell you the performance" has been true since Kaby Lake R, when Intel first moved to quad-cores.

    Look at the massive score variation between i5-8250U CPUs:

    There is genuinely no "one benchmark score". These might as well be different process nodes and in wildly different places in the product stack. It's impossible to know what power limits have been chosen.

    Ever since laptops became thermally constrained, every notebook's TDP (PL1) / PL2 / Tau and thus performance is completely configurable and not standardized.

    This blame also should go back to laptop manufacturers, as well, who damn well know the TDP (PL1) / PL2 / Tau that they explicitly programmed and designed around.

    HP picks a 35 W PL2. Dell picks a 50 W PL2. Acer's Efficiency mode, if chosen, sets a 25 W PL2.

    In the end, I hope AMD sticks it to Intel by demanding AMD OEM manufacturers to clearly label their long-term and short power limits. Nothing but competition will force Intel to change.
  • Spunjji - Friday, September 25, 2020 - link

    This. 👍

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