The AnandTech Decoder Ring for Intel 10nm

The reason why I’m writing about this topic is because it is all a bit of a mess. Intel is a company so large, with many different business units each with its own engineers and internal marketing personnel/product managers, that a single change made by the HQ team takes time to filter down to the other PR teams, but also filter back through the engineers, some of which make press-facing appearances. That’s before any discussions as to whether the change is seen as positive or negative by those affected.

I reached out to Intel to get their official decoder ring for the 10++ to new SuperFin naming. The official response I received was in itself confusing, and the marketing person I speak to wasn’t decoding from the first 2018 naming change, but from the original pre-2017 naming scheme. Between my contacts and I we spoke over the phone so I could hear what they wanted to tell me and so I could tell them what I felt were the reasons for the changes. Some of the explanations I made (such as Intel not wanting to acknowledge Ice Lake 10nm is different to Cannon Lake 10nm, or that Ice Lake 10nm is called that way to hide the fact that Cannon Lake 10nm didn’t work) were understandably left with a no comment.

However, I now have an official decoder ring for you, to act as a reference for both users and Intel’s own engineers alike.  

AnandTech's Decoder Ring for Intel's 10nm
Product 2020+ First
Update
Original
 
Cannon Lake - - 10nm
Ice Lake
Ice Lake-SP
Lakefield (compute)
Snow Ridge
Elkhart Lake
10nm 10nm 10+
Tiger Lake
SG1
DG1
10nm
Superfin
10+ 10++
Alder Lake
First Xe-HP GPU
Sapphire Rapids
10nm
Enhanced
SuperFin
10++ 10+++

For clarity, 10nm Superfin is often abbreviated to 10SF, and 10nm Enhanced Superfin to 10ESF.

Moving forward, Intel’s communications team is committed to explaining everything in terms of 10nm, 10SF, and 10ESF. I have been told that the process of moving all internal documents away from the pre-2017 naming to the 2020 naming is already underway.

We reached out for Intel for a comment for this article:

It is widely acknowledged within the industry that there is inconsistency and confusion in [our] nanometer nomenclature.  Going forward, we will refer the next generation 10nm products as 10nm SuperFin technology-based products.

My take is that whoever had the bright idea to knock Ice Lake down from 10+ to 10 (and then Tiger from 10++ to 10+ etc.), in order to protect the company from addressing issues with the Cannon Lake product, drastically failed at predicting the fallout that this name change would bring. Sometimes a company should accept they didn't score as well as they did, admit the hit, and move on, rather than try and cover it up. So much more time and effort has been lost in terms of communications between the press and Intel, or the press and engineers, or even between the engineers and Intel's own communications team. Even the basic understanding of dealing with that change has been difficult, to the detriment of the press trying to report on Intel’s technology, and likely even on the financial side as investors try to understand what’s going on.

But, truth be told, I’m glad that Intel moved away from the ++++ nomenclature. It allows the company to now easily name future manufacturing node technologies that aren’t just for pure logic performance, which may be vital if Intel ever wants to become a foundry player again.

10nm Changes Direction, Twice
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  • FunBunny2 - Friday, September 25, 2020 - link

    "Intel had a problem with multiplication"

    have they gone back to the future: mult by add in a do-loop? :)
  • Hulk - Friday, September 25, 2020 - link

    Multiplication is really just recursive addition so this makes sense.
  • sharathc - Friday, September 25, 2020 - link

    A typical meeting talks at Intel:

    Engr 1: We have some improvements planned for 14++++++

    Engr 2: Aaaaaaaaam. That should be 14+++++++

    Manager 1: I lost track. How many plusses guys?

    Engr 1: That's 7 + sir.

    Engr 2: Did you say 7? (whaaaaa! he said 6 +)

    Architect: Let us dump 6 and 7 Plusses. From tomorrow, I have 14+++++++++.
  • dotjaz - Friday, September 25, 2020 - link

    Except none of those + nodes actually shrink feature size or add a dimension, therefore changing the number makes zero sense even as a joke.
  • dwbogardus - Friday, September 25, 2020 - link

    None of us are privy to exactly what each of those incremental refinements were, but they did gradually result in higher performance and/or improved yields, both of which are worthy achievements. Even though Intel's 10 nm started out poor, if they are equally persistent in their refinements, it will end up performing very well. But by then, the competition will have moved on from 7 nm to 5 nm. Intel needs to pick up the pace. How does TSMC do it so well, and so quickly?
  • xenol - Friday, September 25, 2020 - link

    Process node names, at least the number, have lost their meaning anyway.
  • Teckk - Friday, September 25, 2020 - link

    Nice article!
    Ian, wait until you have a Super Enhanced Enhanced SuperFin nodes. That'll be fun.
    Probably the first table where I've seen a 10+ as original followed by 10 without the + as the NEXT gen !
  • RSAUser - Saturday, September 26, 2020 - link

    Super Enhanced Enhanced SuperFin++*
  • drexnx - Friday, September 25, 2020 - link

    should have just called it 10.0, 10.1, 10.2, etc. or 10r1, 10r2, 10r3, etc.

    the problem with the plusses wasn't the numerical incrementing, it was that past 3 of them it gets hard to parse the exact number quickly since they're repeating shapes, in addition to the "++ = +1" thing around any computer topic.
  • Flunk - Friday, September 25, 2020 - link

    Should just call it what it is, 14nm. the +s mean nothing.

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