N1 Hyperscale Reference Design

A big part of what is defining the N1 Platform as an actual platform, is the fact that Arm is offering a full reference design with a set of IPs that is fully validated by Arm themselves.

Here we see three reference designs, a Neoverse N1 hyperscale design, which we’ll get into more detail shortly, an N1 edge design, and a Neoverse E1 edge design. Arm’s goals with the reference designs is to give vendors “sweet-spot” configuration options that they will then be able to implement with (relatively) minimal effort.

The N1 hyperscale design is what we’ll be covering in more detail as this represents Arm’s most cutting-edge and competitive product.

As covered on the previous page, at the heart we find the Neoverse N1 CPU in either 64 or 128 core configurations, integrated in a CMN-600 mesh network with either 64 or 128MB of SLC cache. We also see 128 lanes for PCIe 4 respectively CCIX interfaces which provide plenty of I/O bandwidth.

In terms of memory controllers, Arm employs 8x DD4 interfaces up to 3200MHz. Arm actually has abandoned development of its own memory controllers as customers in most cases opted for their own in-house designs or rather opted to choose IP from other third-party vendors such as Cadence or Synopsys. For the current reference designs Arm’s own DMC-520 was still up-to-date and a well-understood block for the company, although in the future newer memory controllers such as for DDR5 will have to rely on third-party IP. Naturally, the reference design targets the latest 7nm process node.

The physical implementation of the SoC would use replicable hierarchical building blocks for ease of design. A “CPU Tile” consists of the two N1 CPU cores, a slice/bank of the SLC cache as well as part of the CMN’s cross points and home-nodes. This CPU Tile is replicated to generate a “Super Tile”, what is added here is peripheral parts of the SoC such as I/O as well as memory controllers. Finally, replicating the super tile in flipped and mirrored implementations results in the final top-level mesh that is to be implemented on the SoC.

Scaling the design to 128 cores doesn’t represent an issue for the IP, although we’ll be hitting some practical limits in terms of current generation technology. Arm’s 64 core N1 reference design with 64MB of cache on a 7nm process node would result in a die size a little under 400mm², which probably is on the higher end of what vendors would want to target in terms of manufacturability. To alleviate such concerns, Arm also took a page out of AMD’s book and floated the idea of chiplet designs, where each chiplet would communicate over CCIX links. Inherently it’s up to the vendor to decide how they’ll want to design their solution, and Arm provides the essential building blocks and flexibility to enable this.

SmartNIC integration capability is also an important aspect of the design and its flexibility. To maximise compute capacity in large scale system, having accelerated network connectivity is key in actually achieving high throughput in the densest (and efficient) form-factor possible.

The CMN-600 allows for slave ports on its crosspoints: Here we can see MMUs connected with high bandwidth interfaces of up to 128GB/s. Attaching fixed-function hardware offloading IP thus would be extremely easy to implement.

CCIX is extremely important for Arm as it enables its product portfolio to integrate with third-party IP offerings. Enabling cache coherency for external IP blocks is an incredibly attractive feature to have as it massively simplifies software design for the vendors. Essentially what this means is that software simply sees a single huge block of memory, whereas non-coherent systems require drivers and software to be aware and track what part of memory is valid and what isn’t. In terms of IP integration, Arm provides the CCIX coherent gateway that integrates with the CMN-600, while on the other side it’s the onus of the third-party IP provider to provide the CCIX translation layer.

Currently Xilinx will be among the first vendors to offer CCIX-enabled end-products in Q3 2019. With AMD also fully embracing CCIX, there’s some very exciting future potential for third-party accelerator hardware, and we be seeing new use-cases that just weren’t feasible before.

Power/Performance management

While it’s a bit weird to talk about power management in the context of implementation scalability (The average reader might think of it as a thermal/cooling consideration), there’s some very interesting implications in terms of how Arm simplifies the work needed to be done by the vendor.

Along a chip’s logical design, a vendor must also implement a power delivery network that will be able to adequately support the IP. In real-world use-cases this means that the PDN needs to be as robust as to deal with the worst-case power scenario of a component. This is actually quite a headache for many vendors as the design requires complex models and in most cases the PDN will need to be over-engineered in order to offer guarantees of stability, which in turn raises the complexity and cost of the implementation.

Arm seeks to alleviate these concerns by offering extremely fine-grained DVFS mechanisms in the form of a dedicated micro-controller. The controller access detailed activity monitoring units inside the CPU cores, seeing what actual blocks and how many transistors are actually actively switching, and feeding this information back to the system controller to change DVFS states. This provides a certain level of hard-guarantee as to when the CPU enters power-virus-like workloads which can cause current spikes, and avoid them in time. This enables vendors to design their PDNs to more conservative tolerances, saving on implementation cost.

The Neoverse N1 CPU: No-Compromise Performance Performance Targets: What Are The Numbers
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  • platinumjsi - Thursday, February 21, 2019 - link

    Wouldnt mind seeing an Anadtech article detailing the differences between X86 and Arm and explaining the benefits and downsides of each architecture.
    Looking at this if ARM can do 64 cores for 105w I have to wonder why it takes AMD 250w on the same process?
    Intel / AMD should be seriously worried about this.

    Could we see ARM-based Laptops / Desktops? Wouldnt be any good for gaming as I cant see devs recompiling there back cataloge for ARM but for Office use these seem ideal.
  • SarahKerrigan - Thursday, February 21, 2019 - link

    ARM laptops already exist, running Windows. Look at the Asus NovaGo or the Lenovo Yoga C630.
  • edzieba - Thursday, February 21, 2019 - link

    ARM still has to overcome the same issue that killed off every other HPC architecture (barring POWER just about hanging in there): not being x86 ( http://3s81si1s5ygj3mzby34dq6qf-wpengine.netdna-ss... ).
  • Antony Newman - Thursday, February 21, 2019 - link

    Perhaps this will all change when Apple move over to an ARM ISA? Apple would have to offer a system that is at least as capable as x86 with a significantly lower lower TCO. I think the limitation up until know was the wimpiness of the ARM offerings; the offerings were cheap but not performant.
  • javadesigner - Friday, February 22, 2019 - link

    What does the "A" in ARM stand for ? I always thought it was Apple. Does Apple make any licensing money when Samsung makes an (A)pple(R)(M) chip ?
  • TobiWahn_Kenobi - Saturday, February 23, 2019 - link

    Acorn RISC Machines
  • TobiWahn_Kenobi - Saturday, February 23, 2019 - link

    Nowadays Advances RISC Machines.
  • darkich - Sunday, February 24, 2019 - link

    .. Isn't this basically (as expected) an expansion of the Cortex A76 architecture?
  • techbug - Sunday, June 9, 2019 - link

    intel w-3175x's rate score doesn't look right. Its single-thread score is 48.18 and 56T is 729.82. So each thread only contributes only 729.82/56=13.03, which seems to be too low.
  • obi210 - Sunday, February 2, 2020 - link

    A Neoverse E1 derivative, without SMT, could be the next gen Arm little core. Such a core with Armv9 support could provide near A73 performance. In-order A53 derivatives should not be carried over to next gen.

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